From c60552c9a1e2f426ec89831ba0f1c3573693ad76 Mon Sep 17 00:00:00 2001 From: Keir Fraser Date: Wed, 9 Jun 2010 14:38:30 +0100 Subject: [PATCH] x86 mce: Use MSR_IA32_MCx_* macros consistently Signed-off-by: Christoph Egger --- xen/arch/x86/cpu/mcheck/amd_k8.c | 4 ++-- xen/arch/x86/cpu/mcheck/k7.c | 12 ++++++------ xen/arch/x86/cpu/mcheck/mce.c | 16 ++++++++-------- xen/arch/x86/cpu/mcheck/mce.h | 2 +- xen/arch/x86/cpu/mcheck/mce_intel.c | 6 +++--- xen/arch/x86/cpu/mcheck/vmce.c | 2 +- 6 files changed, 21 insertions(+), 21 deletions(-) diff --git a/xen/arch/x86/cpu/mcheck/amd_k8.c b/xen/arch/x86/cpu/mcheck/amd_k8.c index 9d5e6913b7..9fc32d6275 100644 --- a/xen/arch/x86/cpu/mcheck/amd_k8.c +++ b/xen/arch/x86/cpu/mcheck/amd_k8.c @@ -90,8 +90,8 @@ enum mcheck_type amd_k8_mcheck_init(struct cpuinfo_x86 *c) mcequirk_amd_apply(quirkflag); } else { /* Enable error reporting of all errors */ - wrmsrl(MSR_IA32_MC0_CTL + 4 * i, 0xffffffffffffffffULL); - wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL); + wrmsrl(MSR_IA32_MCx_CTL(i), 0xffffffffffffffffULL); + wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL); break; } } diff --git a/xen/arch/x86/cpu/mcheck/k7.c b/xen/arch/x86/cpu/mcheck/k7.c index 343b38bdd8..7b5ea16dc9 100644 --- a/xen/arch/x86/cpu/mcheck/k7.c +++ b/xen/arch/x86/cpu/mcheck/k7.c @@ -32,7 +32,7 @@ static fastcall void k7_machine_check(struct cpu_user_regs * regs, long error_co smp_processor_id(), mcgsth, mcgstl); for (i=1; imc_status); + mca_rdmsrl(MSR_IA32_MCx_STATUS(bank), mib->mc_status); mib->common.type = MC_TYPE_BANK; mib->common.size = sizeof (struct mcinfo_bank); @@ -172,11 +172,11 @@ static struct mcinfo_bank *mca_init_bank(enum mca_source who, addr = misc = 0; if (mib->mc_status & MCi_STATUS_MISCV) - mca_rdmsrl(MSR_IA32_MC0_MISC + 4 * bank, mib->mc_misc); + mca_rdmsrl(MSR_IA32_MCx_MISC(bank), mib->mc_misc); if (mib->mc_status & MCi_STATUS_ADDRV) { - mca_rdmsrl(MSR_IA32_MC0_ADDR + 4 * bank, mib->mc_addr); + mca_rdmsrl(MSR_IA32_MCx_ADDR(bank), mib->mc_addr); if (mfn_valid(paddr_to_pfn(mib->mc_addr))) { struct domain *d; @@ -287,7 +287,7 @@ mctelem_cookie_t mcheck_mca_logout(enum mca_source who, struct mca_banks *bankma if (!mcabanks_test(i, bankmask)) continue; - mca_rdmsrl(MSR_IA32_MC0_STATUS + i * 4, status); + mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status); if (!(status & MCi_STATUS_VAL)) continue; /* this bank has no valid telemetry */ @@ -345,7 +345,7 @@ mctelem_cookie_t mcheck_mca_logout(enum mca_source who, struct mca_banks *bankma /* By default, need_clear = 1 */ if (who != MCA_MCE_SCAN && need_clear) /* Clear status */ - mca_wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL); + mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL); else if ( who == MCA_MCE_SCAN && need_clear) mcabanks_set(i, clear_bank); @@ -605,10 +605,10 @@ void mcheck_mca_clearbanks(struct mca_banks *bankmask) for (i = 0; i < 32 && i < nr_mce_banks; i++) { if (!mcabanks_test(i, bankmask)) continue; - mca_rdmsrl(MSR_IA32_MC0_STATUS + i * 4, status); + mca_rdmsrl(MSR_IA32_MCx_STATUS(i), status); if (!(status & MCi_STATUS_VAL)) continue; - mca_wrmsrl(MSR_IA32_MC0_STATUS + 4 * i, 0x0ULL); + mca_wrmsrl(MSR_IA32_MCx_STATUS(i), 0x0ULL); } } @@ -1081,7 +1081,7 @@ void intpose_inval(unsigned int cpu_nr, uint64_t msr) #define IS_MCA_BANKREG(r) \ ((r) >= MSR_IA32_MC0_CTL && \ - (r) <= MSR_IA32_MC0_MISC + (nr_mce_banks - 1) * 4 && \ + (r) <= MSR_IA32_MCx_MISC(nr_mce_banks - 1) && \ ((r) - MSR_IA32_MC0_CTL) % 4 != 0) /* excludes MCi_CTL */ static int x86_mc_msrinject_verify(struct xen_mc_msrinject *mci) diff --git a/xen/arch/x86/cpu/mcheck/mce.h b/xen/arch/x86/cpu/mcheck/mce.h index 8e17bc0a5b..033ddcf649 100644 --- a/xen/arch/x86/cpu/mcheck/mce.h +++ b/xen/arch/x86/cpu/mcheck/mce.h @@ -178,7 +178,7 @@ static inline int mce_vendor_bank_msr(uint32_t msr) static inline int mce_bank_msr(uint32_t msr) { if ( (msr > MSR_IA32_MC0_CTL2 && - msr < (MSR_IA32_MC0_CTL + 4 * nr_mce_banks - 1)) || + msr < (MSR_IA32_MCx_CTL(nr_mce_banks - 1))) || mce_vendor_bank_msr(msr) ) return 1; return 0; diff --git a/xen/arch/x86/cpu/mcheck/mce_intel.c b/xen/arch/x86/cpu/mcheck/mce_intel.c index 7d20f4eafd..7dc3f54a9a 100644 --- a/xen/arch/x86/cpu/mcheck/mce_intel.c +++ b/xen/arch/x86/cpu/mcheck/mce_intel.c @@ -965,13 +965,13 @@ static void mce_init(void) { /* Some banks are shared across cores, use MCi_CTRL to judge whether * this bank has been initialized by other cores already. */ - rdmsr(MSR_IA32_MC0_CTL + 4*i, l, h); + rdmsr(MSR_IA32_MCx_CTL(i), l, h); if (!(l | h)) { /* if ctl is 0, this bank is never initialized */ mce_printk(MCE_VERBOSE, "mce_init: init bank%d\n", i); - wrmsr (MSR_IA32_MC0_CTL + 4*i, 0xffffffff, 0xffffffff); - wrmsr (MSR_IA32_MC0_STATUS + 4*i, 0x0, 0x0); + wrmsr (MSR_IA32_MCx_CTL(i), 0xffffffff, 0xffffffff); + wrmsr (MSR_IA32_MCx_STATUS(i), 0x0, 0x0); } } if (firstbank) /* if cmci enabled, firstbank = 0 */ diff --git a/xen/arch/x86/cpu/mcheck/vmce.c b/xen/arch/x86/cpu/mcheck/vmce.c index 353bae4f5b..b2dca25afe 100644 --- a/xen/arch/x86/cpu/mcheck/vmce.c +++ b/xen/arch/x86/cpu/mcheck/vmce.c @@ -454,7 +454,7 @@ int vmce_init(struct cpuinfo_x86 *c) /* Don't care banks before firstbank */ memset(h_mci_ctrl, 0xff, sizeof(h_mci_ctrl)); for (i = firstbank; i < nr_mce_banks; i++) - rdmsrl(MSR_IA32_MC0_CTL + 4*i, h_mci_ctrl[i]); + rdmsrl(MSR_IA32_MCx_CTL(i), h_mci_ctrl[i]); } if (g_mcg_cap & MCG_CTL_P) -- 2.30.2